This invention relates to an integrated circuit, and more particularly to a decoder circuit for a semiconductor memory.
High-speed decoder circuits using transistors or diodes are already known, and are actually used in LSI circuits for memory. For example, a decoder circuit in which transistors are connected as diodes is described on pages 78-79 of the article "Ultra High Speed 1K-Bit RAM with 7.5 ns Access Time" by H. Mukai and K. Kawarada (IEEE International Solid-State Circuits Conference 1977). Such a decoder circuit in the prior art is shown in FIG. 1. This decoder circuit essentially consists of a decoder transistor Q.sub.D and a current switch which is composed of transistors Q.sub.s1 and Q.sub.s2. In this current switch, current I.sub.s flows through either the transistor Q.sub.s1 or Q.sub.s2 depending on the voltage level of an input V.sub.IN1. When all the current switch transistors which are connected to the emitters of a transistor Q.sub.D such as the transistor Q.sub.s1 are off, the output V.sub.out becomes high. There is only one combination in which an off-transistor of the current switch is connected to all the emitters of the transistor Q.sub.D, in the other transistors Q.sub.D at least one emitter being connected to an on-transistor. Therefore, current flows through a resistor R.sub.D to which Q.sub.D is connected and the outputs of the decoders become low-level.
The basic operation of the decoder circuit is such as described above. However, the decoder circuit which consists of current switches (they serve as current sources) (Q.sub.S1, Q.sub.S2 and I.sub.S) and decoder transistors (Q.sub.D) has two serious drawbacks. One is that the gray area for an address input is widened when an address is switched, because the current I.sub.S 's flow from all the decoder transistors when the address input signal is in the transition region. (The transition region of the current switch consisting of transistors Q.sub.S1 and Q.sub.S2 appears to be about two times wider than that of the ordinary current switch.) Another drawback is that since, the decoder line V.sub.IN1 is charged only through the R.sub.D of the selected decoder (high level), the decoder output rises very slowly. (On the other hand the decoder output falls very fast because current I.sub.S --in the steady state flows into it from many transistors Q.sub.D --flows from one decoder transistor Q.sub.D which is at a high level).
A means for solving these problems is a current switch circuit CS, which is composed of transistors Q.sub.C1, Q.sub.C2, Q.sub.E1 and Q.sub.E2.
This art is disclosed in Japanese Patent Laid-Open No. 97347/1978. This is also shown in FIG. 1.
The use of this current circuit CS can remove the above drawbacks because the decoder line V.sub.IN1 or the like is charged by the emitter followers and the decoder output rises very fast.
However, the circuit in FIG. 1 still has a drawback. This is caused by the fact that the structures of the emitter follower transistors Q.sub.E1, Q.sub.E2 and the decoder transistor Q.sub.D have approximately the same characteristics, and thus their forward voltages between the bases and the emitters are approximately the same. That is, even if an emitter follower transistor Q.sub.E1 or Q.sub.E2 makes the decoder line V.sub.IN1 high, the decoder transistor Q.sub.D cannot be completely off, and some part of the current I.sub.L flows from the decoder transistor Q.sub.D. The selection level of the decoder is essentially determined when all the decoder transistors Q.sub.D are completely off, but if current I.sub.L flows from all the decoder transistors Q.sub.D, the selection level (high level) of the decoder is lowered considerably. In this case, the following problems are brought about:
1. The selection level varies depending on the variation of hFE and V.sub.BE.
2. As the selection level (high level) is lowered, the low level must be lowered in correspondence therewith to obtain a required output amplitude. When the power consumption is constant (current I.sub.S is constant), R.sub.D should be increased in order to enlarge the amplitude, whereby the delay time becomes large.
3. Since the high and low levels at the decoder output are both reduced, the voltage margin of the current switches of the decoder circuit (and the sense circuit (not shown)) is substantially reduced.
4. Since the high level of the decoder line is not completely determined by the emitter follower, the threshold characteristic of the address buffer is deteriorated (the gray area is widened).